A number of semiconductor elements are formed on semiconductor substrates and blade dicing has been used as the most common technique of dividing semiconductor elements. Blade dicing is a cracking technique using a ring-shaped dicing saw rotated at high speed. Such a dicing saw is formed by bonding diamond or cubic boron nitride (CBN) particles with a bonding material. On the cut surfaces of semiconductor substrates made of brittle materials such as Si, cracks generally called chipping occur. In general, between semiconductor elements, a dividing area (dicing area) is formed as an area necessary for dividing the semiconductor elements. The width of the area is designed in consideration of a clearance equal to a chipping length in addition to a substantial width of cut made by a dicing saw. Further, in order to reduce chipping in dicing techniques using dicing saws, the quality of machining has been improved by improving and optimizing the specifications of dicing saws, that is, optimizing the grain size and density of diamond particles or bonding materials and so on, and improving and optimizing the conditions of equipment such as a rotation speed, a feed speed, and a depth of cut.
However, in recent years, improvements in the quality of machining using dicing saws have reached a limit. Particularly, as semiconductor processes support finer design rules, chipping is increasingly caused by brittle surface films, an increasing number of wiring layers, and so on. Thus there is a problem that chipping developing from a cut surface to a semiconductor element along a crystal orientation reaches the inside of the semiconductor element and adversely affects the characteristics of the semiconductor element.
In recent years, the configurations of dicing areas have been reexamined to reach a solution to this problem. For example, in a method of reducing chipping during cutting, a modified layer with degraded crystallinity is formed by one of plasma radiation, ion implantation, and laser radiation on a surface of a dicing area, and then dicing is performed on the modified layer.
Referring to FIG. 8, a conventional semiconductor wafer will be described below.
FIG. 8 is a sectional view showing a dicing area in the conventional semiconductor wafer.
In FIG. 8, reference numeral 1 denotes a semiconductor substrate, reference numeral 2 denotes a semiconductor element, reference numeral 3 denotes a dicing area (dividing area), reference numeral 4 denotes a semiconductor element effective area, reference numeral 5 denotes a crystal modified layer, and reference numeral 6 denotes a dicing cut point (dicing cut width). The plurality of semiconductor elements 2 are formed on the semiconductor substrate 1 to form the semiconductor wafer. The semiconductor wafer is divided into the semiconductor elements 2 by dicing to obtain semiconductor devices.
As shown in FIG. 8, the crystal modified layer 5 is formed on a surface of the semiconductor substrate 1 in the dicing area 3, and the dicing cut point 6 including the crystal modified layer 5 is cut off by dicing. Chipping normally occurs on an area where a large stress is applied to a machining point during dicing. Generally, an area where a large stress is applied to a machining point is an interface between materials having different physical properties. For example, when the wafer is made up of only the semiconductor substrate, the maximum stress is applied to the surface of the semiconductor substrate, that is, an interface between the air and the semiconductor substrate. In other words, in the conventional semiconductor wafer, by forming a layer with crystallinity degraded by plasma or ion implantation on the surface of the semiconductor substrate 1, that is, an area where the maximum stress is applied, it is possible to suppress chipping occurring along a crystal axis on the surface of the semiconductor substrate 1 during dicing.